clock terminal meaning in English
时钟脉冲终端
Examples
- The level adjustment circuit 100 lowers the clock signal input to the first clock terminal ck1 by a predetermined value from h level and provides the signal to the gate of the transistor q5
电平调节电路100将送往第一个时钟终端ck1的时钟信号从h电平降低一个预定值，并将此信号送往晶体管q5的输入端。